Package fixpoint_widgets

This package contains widgets and fixpoint descriptions for simulating filter designs with fixpoint arithmetics and for converting filter designs to Verilog using the migen library. These Verilog netlists can be synthesized e.g. on an FPGA.

Hardware implementations for discrete-time filters usually imply fixpoint arithmetics but this could change in the future as floating point arithmetics can be implemented on FPGAs using dedicated floating point units (FPUs).

Filter topologies are defined in the corresponding classes and can be implemented in hardware. The filter topologies use the order and the coefficients that have been determined by a filter design algorithm from the pyfda.filter_designs package for a target filter specification (usually in the frequency domain). Filter coefficients are quantized according to the settings in the fixpoint widget.

Each fixpoint module / class contains a widget that is constructed using helper classes from fixpoint_widgets.fixpoint_helpers. The widgets allow entering fixpoint specifications like word lengths and formats for input, output and internal structures (like an accumulator) for each class. It also contains a reference to a picture showing the filter topology.

The configuration file pyfda.conf lists which fixpoint classes (e.g. FIR_DF and IIR_DF1) can be used with which filter design algorithm. tree_builder parses this file and writes all fixpoint modules into the list fb.fixpoint_widgets_list.

The widgets are selected and instantiated in the widget input_widgets.input_fixpoint_specs.

The input widget pyfda.input_widgets.input_fixpoint_specs constructs a combo box from this list with references to all successfully imported fixpoint modules. The currently selected fixpoint widget (e.g. FIR_DF) is imported from Package fixpoint_widgets together with the referenced picture.

First, a filter widget is instantiated as self.fx_wdg_inst (after the previous one has been destroyed).

Next, fx_wdg_inst.construct_fixp_filter() constructs an instance fixp_filter of a migen filter class (of e.g. pyfda.fixpoint_widgets.fir_df).

The widget’s methods

  • response = fx_wdg_inst.run_sim(stimulus)
  • fx_wdg_inst.to_verilog()

are used for bit-true simulations and for generating Verilog code for the filter.

input_widgets.input_fixpoint_specs

A fixpoint filter for a given filter design is selected in this widget

Widget for simulating fixpoint filters and generating Verilog Code

class pyfda.input_widgets.input_fixpoint_specs.Input_Fixpoint_Specs(parent)[source]

Create the widget that holds the dynamically loaded fixpoint filter ui

eventFilter(source, event)[source]

Filter all events generated by monitored QLabel, only resize events are processed here, generating a sig_resize signal. All other events are passed on to the next hierarchy level.

exportHDL()[source]

Synthesize HDL description of filter

fx_sim_init()[source]

Initialize fix-point simulation:

  • Update the fxqc_dict containing all quantization information
  • Setup a filter instance for migen simulation
  • Request a stimulus signal
fx_sim_set_stimulus(dict_sig)[source]
  • Get fixpoint stimulus from dict_sig in integer format
  • Pass it to the fixpoint filter and calculate the fixpoint response
  • Send the reponse to the plotting widget
process_sig_rx(dict_sig=None, propagate=False)[source]

Process signals coming in via subwidgets and sig_rx

Play PingPong with a stimulus & plot widget:

  1. fx_sim_init(): Request stimulus by sending ‘fx_sim’:’get_stimulus’
  2. fx_sim_set_stimulus(): Receive stimulus from widget in ‘fx_sim’:’set_stimulus’
    and pass it to HDL object for simulation
  3. Send back HDL response to widget via ‘fx_sim’:’set_response’
process_sig_rx_w_i(dict_sig=None)[source]

Input fixpoint format has been changed. When I/O lock is active, copy input fixpoint word format to output word format.

Flag with propagate=True before proceeding in process_sig_rx to allow for signal propagation.

process_sig_rx_w_o(dict_sig=None)[source]

Output fixpoint format has been changed. When I/O lock is active, copy output fixpoint word format to input word format.

Flag with propagate=True before proceeding in process_sig_rx to allow for signal propagation.

resize_img()[source]

Triggered when self (the widget) is resized, consequently the image inside QLabel is resized to completely fill the label while keeping the aspect ratio.

This doesn’t really work at the moment.

update_fxqc_dict()[source]

Update the fxqc dictionary before simulation / HDL generation starts.

wdg_dict2ui()[source]

Trigger an update of the fixpoint widget UI when view (i.e. fixpoint coefficient format) or data have been changed outside this class. Additionally, pass the fixpoint quantization widget to update / restore other subwidget settings.

Set the RUN button to “changed”.

pyfda.input_widgets.input_fixpoint_specs.classes = {'Input_Fixpoint_Specs': 'Fixpoint'}

display name

Type:Dict containing class name

pyfda.fixpoint_widgets.fir_df

Widget for specifying the parameters of a direct-form DF1 FIR filter

class pyfda.fixpoint_widgets.fir_df.FIR_DF_wdg(parent)[source]

Widget for entering word formats & quantization, also instantiates fixpoint filter class FilterFIR.

construct_fixp_filter()[source]

Construct an instance of the fixpoint filter object using the settings from the ‘fxqc’ quantizer dict

dict2ui()[source]

Update all parts of the UI that need to be updated when specs have been changed outside this class, e.g. coefficients and coefficient wordlength. This also provides the initial setting for the widgets when the filter has been changed.

This is called from one level above by pyfda.input_widgets.input_fixpoint_specs.Input_Fixpoint_Specs.

run_sim(stimulus)[source]

Pass stimuli and run filter simulation, see https://reconfig.io/2018/05/hello_world_migen https://github.com/m-labs/migen/blob/master/examples/sim/fir.py

tb_wdg_stim(stimulus, inputs, outputs)[source]

use stimulus list from widget as input to filter

to_verilog()[source]

Convert the migen description to Verilog

ui2dict()[source]

Read out the quantization subwidgets and store their settings in the central fixpoint dictionary fb.fil[0][‘fxqc’] using the keys described below.

Coefficients are quantized with these settings in the subdictionary under the key ‘b’.

Additionally, these subdictionaries are returned to the caller (input_fixpoint_specs) where they are used to update fb.fil[0]['fxqc']

Parameters:None
Returns:
  • fxqc_dict (dict) – containing the following keys and values:
  • - ‘QCB’ (dictionary with coefficients quantization settings)
  • - ‘QA’ (dictionary with accumulator quantization settings)
  • - ‘b’ (list of coefficients in integer format)
update_accu_settings()[source]

Calculate number of extra integer bits needed in the accumulator (bit growth) depending on the coefficient area (sum of absolute coefficient values) for cmbW == ‘auto’ or depending on the number of coefficients for cmbW == ‘full’. The latter works for arbitrary coefficients but requires more bits.

The new values are written to the fixpoint coefficient dict fb.fil[0][‘fxqc’][‘QA’].

update_q_coeff(dict_sig)[source]

Update coefficient quantization settings and coefficients.

The new values are written to the fixpoint coefficient dict as fb.fil[0][‘fxqc’][‘QCB’] and fb.fil[0][‘fxqc’][‘b’].

pyfda.fixpoint_widgets.fir_df.classes = {'FIR_DF_wdg': 'FIR_DF'}

display name

Type:Dict containing widget class name